1. Field of the Invention
The invention relates to a manufacturing method, and relates particularly to a patterning method.
2. Description of Related Art
Along with a goal for higher integration, semiconductor elements are developing towards miniaturized elements, wherein the size of the semiconductor element needs to be reduced to enhance the integration thereof. In order to reduce the size of the semiconductor element, reducing the line width, reducing the line space and increasing the accuracy of the pattern transferring are problems required to be solved. Improving the lithography process is one of the methods to solve the above problem. A smaller line width or line space may be achieved by existing immersion lithography, however if it is desired to achieve an much smaller line width or line space, then an extreme ultraviolet (EUV) exposure technique is required. However, the above exposure technique cannot be used in mass production and requires high equipment costs.
Self-aligned Double Patterning (SADP) is another method for solving the above problem. By forming a first spacer on a side wall of a mask pattern, then removing the mask pattern and forming a second spacer at a side wall of the first spacer, and lastly removing the first spacer, such that the second spacer is used as a mask for performing a patterning process. By SADP, a line width or line space that is smaller than half of the line width or line space of a typical lithography process may be achieved.
However, in traditional SADP, because the right and left sides of the first spacer are not symmetrical, it causes a situation where the shape of the second spacer is affected by the shape of the first spacer when the second spacer is subsequently formed, such that the asymmetry of the left and right sides of the second spacer is more severe. In this way, when patterning process is performed subsequently by using the second spacer as a mask, a pattern cannot be accurately transferred to the material layer that is to be patterned.